1. Field of the Invention
The present invention relates to a solid-state image device, a manufacturing method thereof, and an image capturing apparatus.
2. Description of the Related Art
In recent years, a CMOS image sensor has been widely used for a video camera, a mobile phone, and the like. In addition, since the CMOS sensor can be formed using a CMOS logic-LSI manufacturing process as a base process, power consumption can be decreased as compared to that of a CCD image sensor having a high voltage analog circuit. Furthermore, since the CMOS image sensor can be microfabricated, mass production thereof can be advantageously performed at a low cost. In addition, in a substrate in which the CMOS image sensor is formed, a logic circuit can be incorporated by the same manufacturing process as that of the CMOS image sensor; hence, on-chip fabrication of an image-data processing circuit can also be realized. Accordingly, when the CMOS image sensor is installed together with a digital signal processor (DSP) and/or a static random access memory (SRAM), for example, a mobile-phone camera module can be suitably miniaturized.
For the purpose of microfabrication and increase in operation speed by a CMOS logic process, a stress liner film is used to improve a current drive ability of a transistor. This stress liner film is formed, for example, of a silicon nitride film and has been frequently used from the 65-nm node era (for example, see Japanese Unexamined Patent Application Publication No. 2003-273240).
The stress liner film described above is a film which distorts a channel portion of a transistor by its own stress so as to increase the mobility of an electron or a hole. The direction of stress applied to a PMOS transistor which improves the mobility thereof is shown in FIG. 24A, and the direction of stress applied to an NMOS transistor which improves the mobility thereof is shown in FIG. 24B.
As shown in FIGS. 24A and 24B, the stress direction of the stress liner film for the NMOS transistor does not coincide with that of the stress liner film for the PMOS transistor. For the NMOS transistor, stresses which pull the channel portion in an x direction and a y direction are effective. For the PMOS transistor, a stress which compresses the channel portion in a y direction is effective. As described above, films having internal stresses in opposite directions are effectively used for the respective transistors. The films as described above are called dual stress liner films.
As the process generation advances, development cost is increased, and hence, in order to reduce the cost, it is significantly important to apply existing process techniques and intellectual properties (IP) which are cultivated through the leading edge MOS development to a CMOS image sensor including a peripheral circuit.
However, an increase in flicker noise of a transistor which receives a stress of the stress liner film described above has been reported (for example, see Shigenobu Maeda et al., “Impact of Mechanical Stress Engineering on Flicker Noise Characteristics”, 2004 Symposium on VLSI Technology Digest of Technical Papers, pp. 102 to 103, 2004).
When the stress liner film is simply used in the CMOS image sensor, noise is increased in an amplifying transistor which is disposed in a pixel transistor portion to amplify a photoelectric-converted charge signal. Hence, the stress liner film may cause, in some cases, fatal characteristic degradation of a device which is configured to have a lower noise.
Accordingly, besides the stress liner technique which is used in a high-speed MOS logic process, a technique which reduces noise of a CMOS image sensor portion is also desired at the same time.